Prospects for terabit-scale nanoelectronic memories

Please use the reference material indicated to answer the four questions below. Email me your answers to these questions prior to our class meeting on Monday, March 19.

Describe different techniques used to scale memory devices in Nano electronics. [Nanotechnology] What are the assumptions made about the Memory defects? [Page 4, Prospects for terabit-scale nanoelectronic memories] What is the main archiectectural challenge faced by Hybrid memories? [Page 1, Prospects for terabit-scale nanoelectronic memories] What is a hybrid scaled memory and what are the challenges it brings? [Hybrid Nanometer Scale Crossbar Memories ]