CSC 8400: LECTURES

Storage Systems (Chapter 6)

Interconnection Networks (Chapter 7)

WARNING: At this pint, the lecture notes posted on this page are incomplete and nonsystematic. You cannot rely on these fragmentary notes.

Fundamentals of computer design
(Chapter 1)

What is our course about?

Hardware -> {Technology, Organization}

Our course is about organization

Technology is the subject of other discipines, such as Electrical Engineering.

Electrical Engineering -> {Physics, Chemistry, ...}


Technology stages:

  1. Mechanical (before 1940s)
  2. Electronic (since 1940s):
  • Vacuum tubes (large, burn out, get hot). Relative performance/cost in 1951 --- 1.
  • Transistors (smaller, cooler, more durable). Relative performance/cost in 1965 --- 35.
  • IC (hundreds of tiny components). Relative performance/cost in 1965 --- 900.
  • VLSI (millions of tiny components). Relative performance/cost in 1995 --- 2,400,000.

    Annual performance improvement:

  • 1970-80 --- 25%
  • 1980-85 --- 35% (from transistors to IC)
  • 1985-present --- 50% (from IC to VLSI, + from HLLCA to RISC)

    High level language --[compiler]--> Assembly language --[assembler]--> Machine language

    RISC --- Reduced Instruction Set Computer architectures; dominant since the middle of the 80s
    HLLCA --- High Level Language Computer Architectures; dominant before the 80s

    RISC vs HLLCA:

  • fewer and simpler instructions
  • higher instruction counts (code density)
  • harder to program for a human
  • easier to implement (simple hardware)
  • more open to architectural innovations

    Reasons for the unpopularity of RISC in the past:

  • Programs were written by humans in assembly language
  • Memory consumption was an issue


    Performance -> {Response time (Execution time), Throughput}

    Response (Execution) time =?

    Wall-clock Time (Elapsed time) is the latency to complete a task, icluding events during which the CPU is idle (e.g., waiting for I/O, or serving other processes).

    Elapsed time = CPU time + The rest

    CPU time = User CPU time + System CPU time

    User CPU time is the CPU time spent in the program, and System CPU time is the CPU time spent in the OS performing tasks requested by the program.

    The UNIX command time:

    %time
    0.65u 0.35s 14:13.76 0.1%

    This means that:

  • user CPU time is 0.65 seconds
  • system CPU time is 0.35 seconds
  • elapsed time is 14 minutes and 13.76 seconds
  • the % of of elapsed time that is CPU time is 0.1


    DLX'


  • 32 registers: R0,R1,...,R31

  • R0 always holds 0

  • Data type: words (32-bit integers)

  • Big endian

  • Addressing modes:

    1) Register: R1
    2) Immediate: #32
    3) Displacement: 32(R1)


    How can we simulate the register deferred mode (R1)?


    Answer: 0(R1)



    How can we simulate the absolute mode (1004)?


    Answer: 1004(R0)



    Instruction set:
    Example instruction Name Meaning
    ADD R1, R2, R3 Add Regs[R1] = Regs[R2] + Regs[R3]
    SUB R1, R2, R3 Subtract Regs[R1] = Regs[R2] -- Regs[R3]
    ADDI R1, R2, #32 Add immediate Regs[R1] = Regs[R2] + 32
    LW R1, 32(R2) Load word Regs[R1] = Mem[32+Regs[R2]]
    SW R1, 32(R2) Store word Mem[32+Regs[R2]] = Regs[R1]
    BEQZ R1, #32 Branch equal zero If (Regs[R1]= =0) PC=PC+32
    BNEZ R1, #32 Branch not equal zero If (Regs[R1]!=0) PC=PC+32



    How can we express the "copy R2 to R1" instruction?


    Answer: ADD R1, R2, R0


    What kind of addressing does DLX' use for branches?


    Answer: PC-relative.


    What kind of architecture (by internal storage) is DLX'?


    Answer: Load/store (register-register) GPR.

    INSTRUCTION FORMAT:

    R-type (ADD, SUB):

    Opcode
    6 bits
    000000
    rs1
    5 bits
    00010
    rs2
    5 bits
    00011
    rd
    5 bits
    00001
    func
    11 bits
    00000000000


    I-type (ADDI, LW, SW, BEQZ, BNEZ):

    Opcode
    6 bits
    000000
    rs1
    5 bits
    00010
    rd
    5 bits
    00001
    Immediate
    16 bits
    0000000000010000




    INSTRUCTION ENCODING:


    ADDR1,R2,R3
    Opcoderdrs1rs2

    SUBR1,R2,R3
    Opcoderdrs1rs2

    ADDIR1,R2,#32
    Opcoderdrs1Immediate

    LWR1,32(R2)
    OpcoderdImmediaters1

    SWR1,32(R2)
    OpcoderdImmediaters1

    BEQZR1,#32
    Opcoders1Immediate

    BNEZR1,#32
    Opcoders1Immediate


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