CSC 8400-002

Examination E2

December 7, 2000

PROBLEM 1 [10%] We have a unified cache with the miss rate of 2% and miss penalty of 10 cycles. If 20% of all instructions in our DLX' benchmark are loads or stores, what is the average number of memory stall cycles per instruction?

 

 

PROBLEM 2 [20%] We have a 3-level cache, with the levels L1 (top), L2 and L3 (bottom). Some information is given in the following table:

 

L1

L2

L3

Hit time

 

1 cycle

10 cycles

30 cycles

Local miss rate

 

1%

10%

20%

Global miss rate

     

 

Miss penalty

   

 

200 cycles

  1. [10%] Fill in the blank cells in the above table.
  2. [4%] What is the average memory access time?
  3. [6%] If the base CPI (also called CPIexecution or Ideal CPI) is 2 cycles and 20% of all instructions are loads and stores, what is the real CPI?

Note: The base CPI includes the hit time for L1, but not for L2 or L3. In other words, the base CPI is the CPI as it would be if there were no misses in L1 (and hence in L2 and L3) at all.

 

PROBLEM 3 [20%] Assume the following:

Let W be the memory word whose (physical) address is

0 0000 1111 0000 1111 0000 1111 0100

a) How many blocks are there in memory?

b) How many sets does the cache have?

c) What is the number of the block in which W is sitting?

d) If W is in the cache, in which block frames could it be?

e) How many different blocks map to any particular set?

PROBLEM 4 [16%] Assume the virtual memory size is 4 GB, the physical memory size is 256 MB, and the page size is 512 bytes.

  1. How many entries would a page table have?
  2. How many entries would an inverted page table have?

 

Here is the initial segment of the (normal) page table:

0000111100001111000

1111000011110000111

---

0000000000000000000

---

1111111111111111111

---

1010101010101010101

1111111100000000000

---

 

c) What is the physical address of the word whose virtual address is

0000 0000 0000 0000 0000 1010 0000 0000 ?

    d) Write the address of a word (an arbitrary word) referring to which would cause a page fault.

PROBLEM 5 [8%] What is the difference between the cycle time and the access time? Which of them is longer for DRAM memories and why?

The optimal answer should NOT be more than half a page.

 

 

PROBLEM 6 [10%] Assume we have the following characteristics for a hard disk:

How long would it take to read a sector from the disk?

 

 

PROBLEM 7 [8%] What is the difference between availability and reliability? How can each of these be improved?

The optimal answer should NOT be more than half a page.

 

PROBLEM 8[8%] Briefly but to the point describe what RAID is, how it works and what it improves.