April 10, 2000
PROBLEM 1 [21%]
Your answer to each part of this question should be clear, to the point and concise - not more than a couple of lines long.
a) What is the difference between the write through and the write back policies?
b) What is the difference between the write allocate and the no write allocate policies?
c) In what kind of caches and for what purpose is the "dirty bit" used?
d) What is the main reason that DRAMs are less expensive and have higher capacity than SRAMs?
e) What is the main reason that DRAMs are slower than SRAMs?
f) What is page table and where is it stored?
g) What is TLB (Translation Lookaside Buffer) and for what purpose is it used?
PROBLEM 2 [10%]
MRU is the replacement policy in caches that chooses the most recently used block for replacement.
Saying just the name of that property (principle) would give you a full credit for this question; no explanation is required.
PROBLEM 3 [16%]
Assume the following:
a) What is the block size?
b) How many different blocks map to set 3?
c) How many bits are there in the tag field of the address of a word?
d) If the (physical) address of a word is 18, in which block frames can that word appear?
PROBLEM 4 [6%]
Assume a direct mapped cache only has 2 block frames in it and that the block size is 4 words.
What would be the miss rate for the following code?
1. ADD R1, R1, R1
2. ADD R2, R2, R2
3. ADD R3, R3, R3
4. ADD R4, R4, R4
5. ADD R1, R1, R1
6. ADD R2, R2, R2
PROBLEM 5 [20%]
You have a DLX machine with a unified cache which has the following features:
Assume also that for our benchmark program(s),
What is the real CPI (taking into account memory stalls due to misses)?
PROBLEM 6 [12%]
Consider a machine that has a 2-level cache with the following characteristics:
a) What is the local miss rate in the second level cache?
PROBLEM 7 [15%]
a) Write the formula for average disk access time.