CSC 8400-001

Examination E2

December 5, 2000

PROBLEM 1 [11%] We have a unified cache with the miss rate of 1% and miss penalty of 50 cycles. The base CPI (also called the ideal CPI, or CPIexecution) is 2 cycles. If 10% of all instructions in our DLX' benchmark are loads or stores, what is the real CPI?



PROBLEM 2 [14%] Assume in a DLX' benchmark loads are 10% of all instructions and stores are 5% of all instructions; the read miss rate in the cache is 2% and the write miss rate is 10%. What is the miss rate (without distinguishing between reads and writes), if the cache we are talking about is:

  1. Unified?
  2. A data-only cache (the data part of a split cache)?



PROBLEM 3 [20%] Assume the following:

Let W be the memory word whose (physical) address is

0000 1111 0000 1111 0000 1111 0100

a) How many blocks are there in memory?

b) How many sets does the cache have?

c) What is the number of the block in which W is sitting?

d) If W is in the cache, in which block frames could it be?

e) How many different blocks map to set #5?



PROBLEM 4 [12%] Assume a direct mapped cache has 2 block frames and the block size is 2 words. What is the miss rate for the following code, assuming that the code starts at the address 0?

T1: ADDI R1, R0, #2

T2: ADD R0, R0, R0

T3: ADD R0, R0, R0

T4: ADDI R1, R1, # - 1

T5: BNEZ R1, T2

PROBLEM 5 [15%] The columns of the following table are indexed with one of the three parameters (hit time, miss rate, miss penalty) on which the cache performance depends. The rows are indexed with some changes in the machine that may or may not affect these parameters. It is assumed that when we make such a change, no other changes are made.

Fill in each cell of the table with "-", "+" or "0".

"-" indicates that the change corresponding to the cell would generally negatively affect (worsen) the parameter corresponding the cell; "+" indicates that the change would generally positively affect (improve) the parameter, and "0" indicates that there would be no effect.


Hit time

Miss rate

Miss penalty

Increasing the size of the cache


Increasing associativity


Replacing DRAM by SRAM in main memory


Replacing SRAM by DRAM in the cache


Making the TLB faster




PROBLEM 6 [7%] What is the purpose of having a write buffer in a write-through cache and how does it work?

The optimal answer should be 2-4 sentences long.


PROBLEM 7 [7%] If the disk rotation rate is 7200 RPM, what is the average rotational delay?


PROBLEM 8[7%] What is the difference between synchronous and asynchronous buses? Briefly discuss their advantages/disadvantages. Is a CPU-memory bus typically synchronous or asynchronous?

The optimal answer should NOT be more than half a page.



PROBLEM 9[7%] Briefly explain the difference between polling and interrupt-driven I/O and discuss their advantages/disadvantages.

The optimal answer should NOT be more than half a page.